Semiconductor processors continue to strive to reduce the size of individual electronic components, thereby enabling smaller and denser integrated circuitry. One typical circuitry device is a field effect transistor. Typically, such includes opposing semiconductive source/drain regions of one conductivity type having a semiconductive channel region of opposite conductivity type therebetween. A gate construction is received over the channel region. Such includes a conductive region having a thin dielectric layer positioned between the conductive region and the channel region. Current can be caused to flow between the source/drain regions through the channel region by applying a suitable voltage to the gate.
In some cases, the channel region is composed of a background doped semiconductive substrate, including doped well material thereof, which is also received immediately beneath the opposite type doped source/drain regions. This results in a parasitic capacitance developing between the bulk substrate/well and the source/drain regions. This can adversely affect speed and device operation, and becomes an increasingly adverse factor as device dimensions continue to decrease. Further adverse factors associated with smaller and denser field effect transistor fabrication include source/drain leakage to the substrate, conducting etch stops on very thin gate dielectric layers, and forming contacts with multi-level alignment.
While the invention was motivated in addressing the above issues, it is in no way so limited. The invention is only limited by the accompanying claims as literally worded (without interpretative or other limiting reference to the above background art description, remaining portions of the specification or the drawings) and in accordance with the doctrine of equivalents.